PCIe: True Statements and Overview | Exam 010-151-DCTECH | Cisco

PCIe: True Statements about Supporting Cisco Data Center System Devices

Question

Which two statements about PCIe are true? (Choose two.)

Answers

Explanations

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A. B. C. D. E.

AE.

PCIe stands for Peripheral Component Interconnect Express. It is a high-speed serial computer expansion bus standard that connects the motherboard to various types of peripheral devices, such as network adapters, graphics cards, and storage devices. PCIe was designed to replace the older parallel PCI and AGP bus standards.

A. The PCIe link is built around dedicated unidirectional couples of serial, point-to-point connections known as lanes. This statement is true. A PCIe link consists of one or more lanes, and each lane is a dedicated point-to-point serial connection between two devices. The number of lanes in a link determines the bandwidth available for data transfer. For example, a PCIe x1 link has one lane, while a PCIe x16 link has 16 lanes.

B. You can install a PCI Express x8 adapter into an x4 slot. This statement is also true. PCIe slots are designed to be backward and forward compatible with different PCIe versions and lane configurations. A PCIe x8 adapter can be installed into an x4 slot because the slot provides enough physical space to accommodate the longer adapter card, but only four of the eight lanes will be used.

C. The PCIe standard is a bus-based system in which all the devices share the same bidirectional, 32-bit or 64-bit, parallel signal path. This statement is false. Unlike the older PCI and AGP bus standards, PCIe is a serial point-to-point architecture, meaning that each device has its own dedicated serial link to the root complex, which manages the traffic between devices.

D. The PCIe 1.0 standard doubles the transfer rate compared to PCIe 2.0. This statement is false. The PCIe standard has evolved over time to increase the available bandwidth for data transfer. PCIe 1.0 has a maximum transfer rate of 2.5 Gbps per lane, while PCIe 2.0 doubles that to 5 Gbps per lane. PCIe 3.0 and 4.0 further increase the maximum transfer rate to 8 Gbps and 16 Gbps per lane, respectively.

E. A link that is composed of four lanes is called an x4 link. This statement is true. The PCIe standard uses a naming convention to describe the number of lanes in a link. An x1 link has one lane, an x2 link has two lanes, and so on. A link that is composed of four lanes is called an x4 link, while a link with 16 lanes is called an x16 link.